In network processor based routers and switches, filters can be used to take actions on incoming and outgoing packets. Network processor based routers are defined herein to include field programmable gate array (FPGA) based routers and switches (i.e., routing apparatuses). Examples of such actions include, but are not limited to, routing table mapping, access control list mapping, and the like. These filters use pre-defined fields that are parsed from the incoming packets and/or incoming interfaces and/or entities. Rules are programmed on filters with different values to match on criteria to take some actions. Accordingly, as is shown in FIG. 1, when the number of interfaces (referred to in FIG. 1 as “IF”) belonging to a common group (e.g. VPRN(1) or VPRN(2)) is large and a filter needs to take a common action (e.g., assigning to a respective VPRN routing table) on all these interfaces, a particular rule must be configured on the filter on a per-interface basis.
To date, this approach of configuring individual rules for each interface/entity to get the same group behavior is the best-known solution for configuring filters in network processor based routers and switches to take actions on incoming and outgoing packets. The need for this rule to be configured for each interface (i.e., unique rule per interface) results in undesirable consumption of memory per rule, which can cause performance degradation due to memory resources utilized by rule searching mechanisms. For example, in one embodiment of such filtering functionality, hardware-based CAM (Content Addressable Memory) is used for fast searching mechanism. Undesirably, consuming large numbers of rules in the hardware-based CAM is expensive in terms of memory usage.